module HC_FPGA_Demo_Top
(
    input  CLOCK_XTAL_50MHz,
	input  KEY4,
	input  RXD,
	output TXD,
	output LED0,
	output LED1,
	output LED2,
	output LED3

);



uart_tx#(
 .CLK_FREQ(50000000)
)(
    .clk(CLOCK_XTAL_50MHz),
    .rst_n(KEY4),
    .led({LED3,LED2,LED1,LED0})
);


endmodule
